A reduction in the size of and the self-alignment of the mask windows would permit a merged transistor structure to be formed having a reduced PNP emitter-base diffusion capacitance, a lower upward NPN collector-base capacitance, a lower PNP base series resistance, and an increased probability of avoiding collector-emitter pipe defects. However, the prior art has been unable to form self-aligned contact and guardring windows on the order of one-micron or less across so as to permit the practical formation of a minimum size (self-aligned) merged transistor logic or merged transistor memory device with a minimum number of critical masks and hot processing steps. U.S. Pat. No. 4,009,057 to Brebisson, et al., discloses a process for forming a vertical NPN transistor which employs the step of forming an oxide layer 4, through which all of the contact holes are etched, followed by sequential steps of selectively blocking various combinations of those windows with a photoresist layer 6, and ion-implanting structures through the openings in the photoresist. Brebisson, et al., removes the masking oxide layer and later forms a passivation layer. Brebisson, et al., cannot make a double diffused lateral PNP as a thick oxidation layer 6, around the oxidation impervious nitride masking layers 5, forms the well known "birds-beak" configuration which would consume the lateral PNP base. In addition, the thickness of the oxide layer 4, approximately 6000 Angstroms, would cause the nitride layer 5 to pop off for window sizes of approximately one-micron. Furthermore, the stress in the emitter-base region of the lateral PNP due to the displacement of the nitride layer 5 by the oxide layer 4, would cause increased recombination sites to form thereby degrading the performance of the resulting device, especially in low current operation.
This prior art process is considered an impractical and quite likely unworkable process as may be seen from FIG. 7 where nitride layer 14b2 must be lifted off the oxide layer 4P by means of etching underneath the nitride layer, a questionable process having a low yield.
Copending U.S. Pat. application Ser. No. 829,302 filed D. L. Bergeron, et al., now U.S. Pat. No. 4,110,126, assigned to the instant assignee, shows another method to form micron to submicron windows, which requires a silicon nitride layer and the reoxidation of the guardring.